1. Field of the Invention
The present invention relates to CMOS output buffer circuits and in particular to an integrated CMOS output buffer adaptable for use in transmitting logic signals onto integrated circuit interconnection links including links with lumped load or transmission line characteristic input impedances.
2. Description of the Prior Art
Integrated logic circuit interconnection is provided by output buffer drivers which are typically tristate devices. The three states are a logic 1 state corresponding to a first voltage level, a logic 0 state corresponding to a second voltage level and a floating level between the first and second levels which does not correspond to a logic signal. A common characteristic among a number of prior art output buffers is the presence of distinguishable circuit portions providing pull up of the voltage level on an output terminal and pull down of the voltage level on the output terminal, corresponding to the logic 1 and logic 0 signal levels, respectively. Control logic provides switching of the pull-up and pull-down circuits for connecting the output terminal to a selected voltage level.
In the floating state, the pull-up and pull-down circuits are in a nonconducting state which provides a high impedance with respect to other signals which can appear on the output terminal of the buffer from an interconnection link such as a transmission line.
Integrated logic circuits are now used in a wide variety of electronic systems and operate at a variety of frequencies. The circuit link between integrated circuits can be a relatively short conductive path with a characteristic impedance at the transmission frequency determined by the input impedance of the destination integrated circuit (i.e. a lumped load). Alternatively, the circuit link can be a transmission line with a characteristic impedance of a distributed load.
Where an interconnection is a lumped load, undesirable voltage ground bounce and current ringing are reduced by slowing the rate o rise of the current pulse of the output signal. For a distributed load, i.e. a transmission line, delivery of substantially all of the final drive current at turn on of the pull-up or pull-down driver is preferred for driving the load properly.
Prior art interconnection drivers have either been specific to one or the other of the above types of loads, or they have been devices with compromised output characteristics. An example of such a prior art device is U.S. Pat. No. 4,638,187 for a "CMOS Output Buffer Providing High Drive Current With Minimum Output Signal Distortion", issued Jan. 20, 1987, to Boler et al and assigned to the assignee of the present invention which is directed to an output buffer advantageously used with lumped loads.
Boler et al teach pull-up and pull-down circuits for connecting an output terminal to one of two potential levels. The pull-up circuit includes first and second field effect transistors connected in parallel between an output terminal and a source of a first potential level, and a delay element for delaying turn on of the second field effect transistor with respect to the first field effect transistor. The pull-down circuit provides third and fourth field effect transistors connected in parallel between the output terminal and a source of the second potential level. The nature of the control electrode of the fourth field effect transistor delays turn on of the fourth field effect transistor with respect to the third field effect transistor. The first field effect transistor is of a complementary conductivity type with respect to the second field effect transistor and the third and fourth field effect transistors are of the same conductivity type as the first field effect transistor.
Boler et al achieve turn on delay by two different techniques. The pull-up circuit provides output driver field effect transistors which are complementary devices, with an inverter stage being utilized to delay turn on of the second output driver field effect transistor relative to the first output driver field effect transistor. In the pull-down circuit two n channel field effect transistors provide the output drivers. The pull-down field effect transistors function as a single distributed transistor. A polysilicon gate electrode with a nonnominal resistance per unit length causes turn on to be propagated along the width of the channel of the distributed device, resulting in a graduated turn on of the field effect transistor.